Not applicable.
Not applicable.
1. Field of the Invention
The present invention generally relates to the processing of interrupts within a computer system. More particularly, the present invention relates to the accommodation of multiple levels of interrupts for a single exception handler processor that is not inherently designed to accommodate multiple interrupt levels. More particularly still, the invention relates to an improved interrupt processing technique for use with a disk array controller that includes a single exception handler processor to permit the processor to respond to an interrupt generated during a debug operation although all interrupts have been disabled.
2. Background of the Invention
Computer systems include at least one, and often more than one, central processing unit (xe2x80x9cCPUxe2x80x9d), also referred to as a xe2x80x9cprocessor.xe2x80x9d Processors typically include many input and output signals. Examples include data and address lines, clock lines, power and ground lines, and others. Most processors include at least one xe2x80x9cinterruptxe2x80x9d input signal. An interrupt is a signal generated by a device within the computer system, such as a keyboard, floppy disk drive controller or hard disk drive controller, when that device needs the processor to perform a task. For example, a modem might assert an interrupt when it detects an incoming transmission on the telephone line. Although there are other ways (besides the use of interrupts) for devices in a computer system to request an action, interrupt techniques have been widely used for many years and provide an efficient way to inform the system that an action is required.
The processor responds to an asserted interrupt by stopping execution of the code currently under execution and retrieving an xe2x80x9cinterrupt handler vectorxe2x80x9d which informs the processor of the location of the interrupt code to execute to service the interrupt. The interrupt code is usually referred to as an interrupt handler.
Many processors provide multiple xe2x80x9clevelsxe2x80x9d of interrupts. Accordingly, one or more interrupt signals can be assigned to each level. Some levels may have a higher priority than other levels and thus may be acted upon quicker than the interrupts assigned to lower levels. Each level has programmable characteristics that are separately programmable from those of other levels. For example, one programmable characteristic of an interrupt level is the ability to enable and disable the interrupt signals assigned to that level. Disabling an interrupt means that the processor will not respond to an asserted interrupt signal. Enabling interrupts is the opposite action in which the processor is permitted to respond to an asserted interrupt signal. There are various reasons why interrupts may need to be disabled. For instance, it may be important not to interrupt an action currently being performed by the processor. This may occur when a processor writes a set of data to memory. Other devices in the system may subsequently need access to that data set. If the data write cycle is permitted to be interrupted, the complete data set may not be written to memory before a device interrupts the processor to request access to the data. The processor or other logic can avoid this type of problem by disabling interrupts during the write cycle and then re-enabling the interrupts after the data set is fully written to memory.
With multiple interrupt levels, a computer system can have some interrupts disabled while other interrupts continue to be enabled and available for use. Although many processors have the provision for multiple interrupt levels, not all processors are so equipped. Processors that do not provide multiple interrupt levels have only a single interrupt level and are referred to as xe2x80x9csingle exception interrupt handlerxe2x80x9d processors. An example of such a processor is the PowerPC 600 and 700 series processors provided by IBM. In such a processor all of the interrupts are either enabled or disabledxe2x80x94it is not possible to enable only some of the interrupts. This inability to selectively disable certain interrupts can cause a problem when an interrupt is needed but none are enabled. The following example illustrates such a problem.
A Redundant Array of Independent Disks (xe2x80x9cRAIDxe2x80x9d) storage system typically includes multiple data drives on which data is stored and a parity drive in which parity data is stored. The parity data permits the contents of any one data drive to be calculated in the event that drive becomes non-operational. Such a RAID system is generally known to those of ordinary skill in the art. The system includes a controller board that provides an interface between the computer system and one or more mass storage devices typical of a RAID storage system. The controller board that the system uses to control the various drives includes a single exception interrupt handler processor in which all of the interrupts must be jointly either enabled or disabled. The controller board also includes a serial port through which a communication device, such as a laptop computer, can be connected to debug any problems experienced by the electronics on the board. After or upon connecting the laptop to the controller board, an interrupt is asserted to the controller board""s processor to notify the board that the laptop has been connected and debugging operations are to begin.
If a person connects the laptop to the controller board at a time when the interrupts are disabled, the desired debugging activity will not be permitted to begin. The interrupts may be disabled at a time when a critical action is being performed by the board""s electronics and when a device on the board malfunctions precluding the action from completing. In this instance, the interrupts are disabled when the board is experiencing a problem, but debugging cannot begin to diagnose the problem because the interrupts are disabled. Accordingly, a solution is needed for such a problem.
The problems noted above are solved in large part by a single level interrupt processor on the array controller board that contains a critical failure input line that permits implementation of a nonmaskable pseudo-interrupt for debugging of the array controller. The nonmaskable pseudo-interrupt informs the processor of a debug request even when all device interrupts in the processor are disabled and the array controller board is inoperative. A processor-to-bus bridge connected to the single level interrupt processor on the array controller board contains an interrupt status register, interrupt mask register, and a critical interrupt register. Test equipment is connected to the processor-to-bus bridge through a three pin serial port, the test equipment able to set a bit in the critical interrupt register for requesting the nonmaskable pseudo-interrupt, the processor-to-bus bridge reading the bit in the critical interrupt register to determine whether a nonmaskable pseudo-interrupt has occurred. The processor-to-bus bridge asserts the critical failure input line of the processor after determining that the test equipment has requested the nonmaskable pseudo-interrupt. The processor then executes handler software routines that communicate with the test equipment to debug the array controller board.